Image Signal Processing (ISP) RTL Design Engineer

Uniconnect • Broadband • Verilog • C++ • SystemVerilog • SystemC • 1 year ago
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Salary
≈ $43k – $86k per year (Estimated)
Location
In office (Singapore)
Seniority
Middle · 3+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 26, 2026. First seen by Alion on Mar 27, 2025. Uniconnect scores D on the Alion truth index.

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Uniconnect

Looking for the Top Semiconductor and AI Acquisition Firm in Singapore? UniConnect is your trusted job agency for recruitment solutions in Singapore.
uniconnect.com.sg • Bengaluru • Hyderabad • George Town • Bayan Lepas • Coimbatore • Professional Services • Recruiting & Staffing
  • Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
  • Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
  • Verify Logic at ISP level and Digital System level
  • Optimize Design for less gate count and low power consumption
  • Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

  • Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
  • Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
  • Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
  • Strong debugging and problem-solving skills
  • Good communication and interpersonal skills
  • Result oriented and embrace change behaviours
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