Actively hiring
Digital Storage
Cybersecurity
Consumer Electronics
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Overview
访问兆易创新(GigaDevice)官方网站,探索 Flash、MCU、DRAM、传感器及模拟产品,获取产品数据手册、开发软件、技术文档与行业解决方案,满足产品选型和应用开发需求。.
Tech stack
Technologies named in job postings at Zhaoyichuangara GigaDevice over the last 12 months, by layer, with the share of postings for each.
Technologies in use
14
Postings analysed
14
Stack modernity
73/100
Languages
C++21%
Python21%
SystemVerilog21%
Perl14%
Cloud & platforms
Linux14%
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Full Zhaoyichuangara GigaDevice tech stack
14 technologies · by team · pay by technology · changes · similar stacks
Growth
Hiring Momentum
28/100
Slowing
Open positions
37
0 opened / 0 closed in 30 days
ATS activity
Every ~3 hours
Today
Hiring Focus
The percentage next to each role is its share of the company's job openings over the last 90 days; the arrow shows the shift versus the previous period.
Industrial Engineering
49% ▲
Hardware
26% ▲
Backend
15% ▲
Marketing
5% ▲
AI/ML
3% ▲
Finance
3% ▲
Offices
Where the company hires and what each office is for
Cities
7
Hiring now
7
Countries
1
Busiest office
Beijing
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Headquarters
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Office with open vacancies
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Beijing
China
HQ
11 open roles 11 posted in 90 days 27% engineering
hires for Industrial Engineering, Hardware, Marketing
Xi'an
China
Plant / site
14 open roles 14 posted in 90 days 50% engineering
hires for Industrial Engineering, Hardware, Backend
Hefei
China
Engineering / R&D
7 open roles 7 posted in 90 days 71% engineering
hires for Backend, Hardware, Industrial Engineering
Chengdu
China
Plant / site
3 open roles 3 posted in 90 days 33% engineering
hires for Industrial Engineering, Hardware
Shanghai
China
2 open roles 2 posted in 90 days
hires for Finance, Industrial Engineering
Wuhan
China
1 open roles 1 posted in 90 days 100% engineering
hires for AI/ML
Zhuhai
China
1 open roles 1 posted in 90 days
hires for Industrial Engineering
Jobs
≈ $29k – $84k per year (Estimated) • In office • Full-Time • Xi'an
SystemVerilog
Perl
Formal Verification
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≈ $30k – $87k per year (Estimated) • In office • Full-Time • Chengdu
Verilog
Cadence Virtuoso
Synopsys HSPICE
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