Silicon Design Engineer
Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Oct 14, 2026.
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Senior Formal Verification Engineer - USB
The Role
We are seeking a Senior Formal Verification Engineer to join AMD’s USB Design Verification team in Hsinchu or Taipei. You will develop and execute formal verification strategies for complex USB controller IP and related subsystems.
This is a hands-on technical role with opportunities to influence verification architecture, methodology, and sign-off quality. You will collaborate closely with design, architecture, simulation DV, and other engineering teams to identify high-risk behaviors, prove design correctness, and detect subtle bugs that are difficult to reach through simulation alone.
The Person
The ideal candidate has strong formal verification fundamentals, solid RTL design knowledge, and experience applying formal methods to complex digital designs. You are comfortable owning verification problems independently, debugging counterexamples, and communicating results across teams.
Experience with USB or other high-speed interfaces is preferred, but deep formal verification expertise and the ability to learn new protocols are more important.
Key Responsibilities
- Develop formal verification plans and strategies for USB controller IP and related logic.
- Build and maintain formal testbenches, assertions, assumptions, constraints, and reference models.
- Apply formal methods to protocol control logic, state machines, data integrity, connectivity, ordering, arbitration, and error-handling behaviors.
- Execute property verification, connectivity checking, deadlock analysis, and formal coverage analysis.
- Debug counterexamples and collaborate with RTL designers to identify root causes and corrective actions.
- Define measurable formal sign-off criteria and communicate verification status, gaps, and risks.
- Identify verification areas where formal methods provide greater confidence or efficiency than simulation.
- Improve formal verification methodology, automation, scalability, and reuse across projects.
- Review specifications and microarchitecture documents to identify ambiguities and verification risks early.
- Partner with simulation DV teams to develop complementary formal and dynamic verification strategies.
- Provide technical guidance and mentoring to other engineers.
Preferred Experience
- Strong experience in formal property verification of complex RTL designs.
- Proficiency with SystemVerilog and SystemVerilog Assertions.
- Hands-on experience with formal verification tools such as Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or equivalent.
- Experience developing formal environments, abstractions, constraints, checkers, and coverage models.
- Strong counterexample-debugging and root-cause-analysis skills.
- Solid understanding of digital design, finite-state machines, pipelines, clock/reset behavior, and bus protocols.
- Experience with Verilog/SystemVerilog RTL and scripting languages such as Python, Perl, Tcl, or shell.
- Familiarity with simulation-based verification and UVM.
- Knowledge of USB 2.0, USB 3.x, USB4, xHCI, or another high-speed protocol is an advantage.
- Experience driving verification plans or methodology across multiple engineers is preferred.
- Strong written and verbal communication skills, with the ability to work effectively across global teams.
Academic Credentials
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Relevant industry experience in formal verification, design verification, or RTL design.
Location: Hsinchu or Taipei, Taiwan
- #LI-JW3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Senior Formal Verification Engineer - USB
The Role
We are seeking a Senior Formal Verification Engineer to join AMD’s USB Design Verification team in Hsinchu or Taipei. You will develop and execute formal verification strategies for complex USB controller IP and related subsystems.
This is a hands-on technical role with opportunities to influence verification architecture, methodology, and sign-off quality. You will collaborate closely with design, architecture, simulation DV, and other engineering teams to identify high-risk behaviors, prove design correctness, and detect subtle bugs that are difficult to reach through simulation alone.
The Person
The ideal candidate has strong formal verification fundamentals, solid RTL design knowledge, and experience applying formal methods to complex digital designs. You are comfortable owning verification problems independently, debugging counterexamples, and communicating results across teams.
Experience with USB or other high-speed interfaces is preferred, but deep formal verification expertise and the ability to learn new protocols are more important.
Key Responsibilities
- Develop formal verification plans and strategies for USB controller IP and related logic.
- Build and maintain formal testbenches, assertions, assumptions, constraints, and reference models.
- Apply formal methods to protocol control logic, state machines, data integrity, connectivity, ordering, arbitration, and error-handling behaviors.
- Execute property verification, connectivity checking, deadlock analysis, and formal coverage analysis.
- Debug counterexamples and collaborate with RTL designers to identify root causes and corrective actions.
- Define measurable formal sign-off criteria and communicate verification status, gaps, and risks.
- Identify verification areas where formal methods provide greater confidence or efficiency than simulation.
- Improve formal verification methodology, automation, scalability, and reuse across projects.
- Review specifications and microarchitecture documents to identify ambiguities and verification risks early.
- Partner with simulation DV teams to develop complementary formal and dynamic verification strategies.
- Provide technical guidance and mentoring to other engineers.
Preferred Experience
- Strong experience in formal property verification of complex RTL designs.
- Proficiency with SystemVerilog and SystemVerilog Assertions.
- Hands-on experience with formal verification tools such as Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or equivalent.
- Experience developing formal environments, abstractions, constraints, checkers, and coverage models.
- Strong counterexample-debugging and root-cause-analysis skills.
- Solid understanding of digital design, finite-state machines, pipelines, clock/reset behavior, and bus protocols.
- Experience with Verilog/SystemVerilog RTL and scripting languages such as Python, Perl, Tcl, or shell.
- Familiarity with simulation-based verification and UVM.
- Knowledge of USB 2.0, USB 3.x, USB4, xHCI, or another high-speed protocol is an advantage.
- Experience driving verification plans or methodology across multiple engineers is preferred.
- Strong written and verbal communication skills, with the ability to work effectively across global teams.
Academic Credentials
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Relevant industry experience in formal verification, design verification, or RTL design.
Location: Hsinchu or Taipei, Taiwan
- #LI-JW3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.