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Salary
≈ $53k – $120k per year (Estimated)
Location
Hybrid (Yerevan, Armenia)
Seniority
Senior · 7+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 31, 2026. First seen by Alion on Oct 30, 2026. Cisco Systems scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Cisco Systems is an American networking company founded in 1984 by Stanford computer scientists Leonard Bosack and Sandy Lerner, and headquartered in San Jose, California. It is the largest supplier of enterprise networking equipment in the world, building the routers, switches, wireless access points and optical systems that carry traffic across corporate networks, service providers and data centres, together with the software and silicon that run them. The company has diversified heavily into security, observability through Splunk, collaboration with Webex, and AI infrastructure networking, and now earns a growing share of revenue from software subscriptions rather than hardware sales.

Meet the Team

As part of the team behind Cisco Silicon One-the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers-you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Our international group focuses on groundbreaking process technology to ensure the efficiency and performance of our ASIC products.

Your Impact

As an ASIC Circuit Design Engineer, you will own the end-to-end development of high-performance ASIC subsystems and reusable IP. You will contribute to achieving aggressive power, performance, area, and reliability goals by developing custom digital and analog/mixed-signal blocks. You will work closely with architecture, physical design, and silicon validation teams to ensure our IP is optimized for the next generation of networking silicon, while employing automation to drive quality and productivity across the entire product lifecycle.

Key Responsibilities

  • Drive the architecture, design, and implementation of high-performance ASIC subsystems and IP from specification through silicon validation.
  • Develop and productize standard-cell, custom digital, and analog/mixed-signal IP to meet strict performance and robustness requirements.
  • Perform transistor-level simulation and optimization, accounting for process, voltage, temperature, and aging conditions.
  • Define and implement characterization methodologies for standard-cell and mixed-signal models, including the deployment of automated EDA flows.
  • Collaborate with multi-functional teams, including physical design and system architecture, to define interface requirements and implementation constraints.
  • Own the physical implementation of complex custom blocks, optimizing for timing, power, signal integrity, and layout-dependent effects.
  • Analyze silicon results post-bring-up to drive improvements in circuit design, characterization models, and future IP architectures.
  • Drive technical reviews for schematics, layouts, and methodologies to resolve complex cross-disciplinary issues and mitigate architectural risks.
  • Develop reusable infrastructure, scripts, and documentation to improve engineering productivity and design quality.
  • Apply expertise in advanced process nodes, including FinFET and GAA, to push the boundaries of ASIC power-delivery and clocking solutions.

Minimum Qualifications

  • Bachelor’s degree and 7 years of related experience, or Master’s degree plus 4 years of related experience, or PhD plus 1 year of related experience.
  • Relevant experience should include ASIC, custom digital, standard-cell, or analog/mixed-signal circuit design and implementation.

Preferred Qualifications

  • Design & IP Development: Proven expertise in designing and optimizing custom digital circuits (e.g., standard cells, low-power cells) and analog/mixed-signal IP (e.g., regulators, oscillators, sensors) with a strict focus on PPA, reliability, and yield.
  • Methodology & Analysis: Strong background in circuit-level analysis (SPICE, PVT, Monte Carlo, variation) and standard-cell modeling (Liberty, CCS/ECSM, LVF) using industry-standard EDA tools from Cadence, Synopsys, or Siemens.
  • Physical & Process Implementation: First-hand experience with advanced nodes (FinFET/GAA) and physical implementation flows, including custom layout, parasitic extraction, DRC/LVS, and reliability analysis (EM/IR).
  • Silicon Lifecycle & Leadership: Demonstrated ability to lead technical reviews, influence ASIC architecture, and get results through silicon bring-up, failure analysis, and model-to-silicon correlation.
  • Proficiency in automation and scripting (Python, Tcl, or shell) to enhance engineering productivity.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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