2,049,612open jobs
120,684companies
244,001added this week
Browse all
Salary
$155k – $250k per year
Location
Hybrid (Santa Clara, United States)
Seniority
Staff · 5+ years exp
Visa
H-1B filings in 12 months: 2 · green card filings: 1
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 29, 2026. First seen by Alion on May 20, 2025. d-Matrix scores A on the Alion truth index.

Overview
Company
Impact
Profile match
d-Matrix is a semiconductor technology company based in Santa Clara, California, and was founded in 2019. The company develops specialized AI inference hardware and software platforms, including its Corsair platform and 3DIMC architecture, designed to accelerate generative AI workloads in data centers. It operates as a venture-backed enterprise serving global hyperscalers and enterprises with a focus on reducing latency, power consumption, and total cost of ownership for large language models.
Backed by Playground, M12, IPO Club

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

Role Overview

d-Matrix is looking for a Staff Analog Design Engineer to lead analog-mixed signal IC design for our next-generation AI inference accelerators. This role owns circuit design for two critical subsystems: our in-memory-compute engine and the die-to-die serial interface that enables scale-out. You will drive design from schematic through silicon bring-up, guiding layout engineers working in deep sub-micron process nodes (7nm and below) and ensuring designs meet low-power performance targets across process-voltage-temperature corners. You will partner closely with layout engineers, backend/digital integration teams, and cross-site colleagues to deliver silicon-ready designs. This is a high-impact role for someone who wants to shape the analog foundations of state-of-the-art AI hardware.

What You Will Do

  • Design analog-mixed signal circuits using industry-standard tools such as Cadence and Synopsys

  • Develop schematic-level circuit designs and conduct system-level performance analysis

  • Build test benches to support simulation and verification, including Monte Carlo yield analysis across PVT corners

  • Guide layout engineers on circuit layout in deep sub-micron process nodes (7nm and below), including hands-on minor layout adjustments as needed

  • Partner with backend engineers to integrate design and layout, and provide circuit models to support backend verification

  • Support testboard design for silicon bring-up, bench debug, and characterization

  • Build scripts to support silicon bring-up and test feature validation

What You Will Bring

  • BS, MS, or PhD in Electrical Engineering with 5+ years of related professional experience in high-speed circuit design (e.g., phase interpolators, clocking, PLL design)

  • Experience with schematic capture, SPICE simulation, and Monte Carlo simulation

  • Experience with circuit layout, extraction, and back-annotated simulation

  • Experience with channel modeling using MATLAB or similar tools

  • Strong cross-functional communication and collaboration skills, with the ability to work effectively across distributed, cross-site teams

  • Strong analytical and problem-solving skills, with the ability to manage multiple priorities in a fast-paced environment

Preferred Qualifications

We'd be excited about candidates with deep expertise in any one of the following areas:

  • SerDes verification & characterization - building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)

  • Clocking & CDR - ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architectures

  • TX/RX datapath - high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architectures

  • Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participation

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
2,049,612 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Industrial Engineering
Similar stack
Same company
Santa Clara
$47k – $70k per year · In office · 5+ years exp · High School Diploma · California City
Apply
≈ $77k – $145k per year (Estimated) · In office · 5+ years exp · High School Diploma · Rock Hill
Apply
≈ $153k – $289k per year (Estimated) · In office · 10+ years exp · Bachelor's Degree · Memphis
Apply
$69k – $95k per year · In office · Full-Time · 5+ years exp · Carlsbad
Apply
≈ $87k – $165k per year (Estimated) · In office · Full-Time · 5+ years exp · Austin
Apply
≈ $87k – $191k per year (Estimated) · In office · Full-Time · 2+ years exp · Indianapolis
Python
C++
MATLAB
AI/ML
Computer Vision
Machine Learning
DevOps
Linux
Robotics
ROS
Gazebo
Webots
ArduPilot
MAVLink
SLAM
Sensor Fusion
Apply
≈ $15k – $34k per year (Estimated) · Remote (India) · 3+ years exp · Bengaluru
C
C++
MATLAB
C
Embedded C
MATLAB
Simulink
DevOps
RTOS
Git
Apply
Remote (likely United States) · Full-Time
Python
C++
Julia
MATLAB
Julia
SciML
JuliaHub
AI/ML
AI Agents
Machine Learning
Apply
$152k – $234k per year · Equity · In office · TS/SCI · 5+ years exp · Bachelor's Degree · Long Beach
MATLAB
SpaceTech
STK
Apply
≈ $8k – $21k per year (Estimated) · In office · 2+ years exp · India
Python
MATLAB
Apply
$175k – $265k per year · Hybrid · Full-Time · 7+ years exp · Bachelor's Degree · Santa Clara
Design
SolidWorks
SpaceTech
Siemens NX
ANSYS
Apply
$175k – $265k per year · Hybrid · Full-Time · 15+ years exp · Bachelor's Degree · Santa Clara
SpaceTech
GD&T
Apply
$175k – $265k per year · Hybrid · Full-Time · 10+ years exp · Bachelor's Degree · Santa Clara
Python
Chips/EDA
Cadence Allegro
Apply
Hybrid · Full-Time · 2+ years exp · Belgrade
Python
C++
AI/ML
Quantization
DevOps
Linux
Apply
$195k – $285k per year · Hybrid · Full-Time · 15+ years exp · Bachelor's Degree · Santa Clara
Chips/EDA
Statistical Process Control
Management
Agile
SpaceTech
FMEA
MedTech
CAPA
Apply
≈ $43k – $75k per year (Estimated) · In office · Part-Time · San Jose · Santa Clara · Sunnyvale · Cupertino · Mountain View
Apply
≈ $43k – $75k per year (Estimated) · In office · Part-Time · San Jose · Santa Clara · Sunnyvale · Cupertino · Mountain View
Apply
≈ $49k – $102k per year (Estimated) · In office · Part-Time · San Jose · Santa Clara · Sunnyvale · Cupertino · Mountain View
Apply
≈ $43k – $75k per year (Estimated) · In office · Part-Time · San Jose · Santa Clara · Sunnyvale · Cupertino · Mountain View
Apply
≈ $43k – $75k per year (Estimated) · In office · Part-Time · San Jose · Santa Clara · Sunnyvale · Cupertino · Mountain View
Apply
See all jobs
This is one of many
2,049,612 more open roles from verified company boards, updated every day.