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Salary
$111k – $208k per year
Location
Hybrid (Moorestown, United States)
Seniority
Staff · 9+ years exp
Visa
H-1B filings in 12 months: 1

Confirmed on the employer's own hiring board on Nov 3, 2026. First seen by Alion on Oct 13, 2026. Lockheed Martin scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Lockheed Martin is the largest defence contractor in the world, formed in 1995 by merging Lockheed Corporation with Martin Marietta and headquartered in Bethesda, Maryland. Its single most important programme is the F-35 Lightning II, the most expensive weapons system ever built, alongside the F-16, the C-130 transport and classified work at the Skunk Works advanced development unit. The company also dominates missile defence with THAAD and PAC-3 interceptors, supplies HIMARS and Javelin systems, owns the helicopter maker Sikorsky, and builds the Orion crew capsule and military satellites through its space division.

Standard Job Description

What We're Doing

You will be a Lead ASIC Digital Design Engineer for the IC Design Team at Lockheed Martin Rotary Mission Systems (RMS). Our team delivers precision engagement aerospace and defense systems, designing, building and fielding the electrical hardware that support sensors and other mission critical subsystems for the United States and allied militaries.

The Work

As a Lead ASIC Digital Design Engineer you will own the full physical-design flow - from floorplan through tape-out - serving as the technical lead who turns schematic intent into high-performance, parasitic-aware physical designs across a portfolio of programs. You will operate in an environment primarily using Cadence EDA tools and drive physical-verification closure across multiple foundries in direct support of mission-critical programs. Your responsibilities will include:

  • Leading full-custom digital, analog, and mixed-signal design across multiple programs, from architectural design, RTL synthesis, floor-planning through place-and-route and verification of digital and analog blocks, optimizing area, device matching, signal integrity, and power delivery.
  • Owning the physical-design technical strategy for device generations from 130 nm to 12 nm, including high-voltage BCD processes, and driving layout methodology standardization across the department.
  • Lead technical teams, mentor staff engineers, and influence design direction across organizational boundaries

Why Join Us

Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you.

We offer flexible work schedules to comprehensive benefits investing in your future and security. Learn more about Lockheed Martin’s comprehensive benefits package here.

Basic Qualifications

  • Bachelor’s degree or higher in Electrical Engineering, Electronics Technology, Microelectronics, or a related technical discipline
  • Minimum 9 years of experience in full-custom digital or mixed-signal IC layout design
  • Expert-level proficiency with the Cadence Innovus and Virtuoso layout environment
  • Experience with RTL coding (VHDL, Verilog, System Verilog)
  • Layout experience across process nodes including BCD technologies
  • Experience driving physical-verification closure with test benches (DRC, LVS, ERC, ANT) to sign-off across multiple foundry processes
  • Ability to obtain and maintain a DoD Secret clearance requires US Citizenship

Desired Skills

  • Demonstrated experience as the physical-design / layout technical lead on a major effort, with responsibility for floor plan through tape-out of complex digital, analog, and mixed-signal ICs
  • Layout experience with precision analog blocks such as PLLs, ADC/DACs, LDOs, bandgap references, or amplifiers
  • Experience owning tape-out sign-off packages and chairing physical-design review gates on concurrent programs
  • Excellent verbal and written communication skills with demonstrated ability to brief leadership, customers, and non-technical audiences
  • Strong mentoring track record with mid-career and staff-level layout engineers
  • Successful proposal/capture contribution experience (BOE, technical-volume authoring, technical strategy) on major IC programs
  • Previous experience related to aerospace/defense IC design techniques

Pay Information

  • $110500.00 - $208344.00

At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow-both professionally and personally.

The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only.

Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.

Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.

  • Additional specific benefits are dependent upon the business unit and the collective-bargaining agreement.
  • Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.
  • For (Washington state applicants only) Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.
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