ASIC Frontend Design Engineer

ASIC Frontend Design Engineer:

Work Location: Kolkata (3 days WFO)

Experience: 1) Engineer (5-12 years & IC role), 2) Manager (14-20 years)

Mode of Interview: 2 Rounds Virtual followed by last F2F at Bangalore or Kolkata office.

Opportunity Snapshot:

We are looking for a highly skilled ASIC Frontend Design Engineer to join our high-performance VLSI team. You will be responsible for designing and delivering next-generation, high-speed ASICs for complex networking and compute systems, while collaborating with global Architecture, Design, Verification, and Physical Design teams. We foster a culture of innovation, ownership, collaboration, and continuous learning, offering excellent opportunities for technical growth and leadership.

Key Responsibilities:

- Design and develop high-performance ASICs and SoC blocks for next-generation products.

- Define microarchitecture, perform RTL design, and optimize for performance, power, and area (PPA).

- Develop high-quality RTL using Verilog/SystemVerilog.

- Collaborate with Verification teams on test planning, functional coverage, debug, and verification closure.

- Work with Physical Design teams on timing constraints, timing analysis, and timing closure.

- Participate in design reviews, root-cause analysis, and silicon bring-up activities.

- Drive cross-functional collaboration with Architecture, Verification, Firmware, Physical Design, and Program Management teams.

Required Skills:

- Strong RTL coding expertise in Verilog/SystemVerilog.

- Good understanding of SoC architecture, microarchitecture, digital logic, and ASIC design.

- Hands-on experience with SystemVerilog, UVM, SVA, coverage-driven verification, and RTL concepts.

- Knowledge of high-speed protocols such as PCIe, Ethernet, AXI, NoC, DDR/HBM, CXL, UCIe, or cache coherency protocols.

- Experience with high-performance memory subsystems, clock-domain crossing (CDC), and high-speed serial interfaces.

- Familiarity with Synopsys Design Compiler, Formality/LEC, SpyGlass, and other EDA tools is preferred.

- Strong debugging, analytical, and problem-solving skills with excellent written and verbal communication.

Preferred Qualifications:

- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, Microelectronics, VLSI, or a related discipline.

- Experience in networking ASICs, storage, AI/ML accelerators, or high-performance SoCs is highly desirable.

Skills

VLSI, ASIC, RTL Design, Verilog, SoC, System Verilog, Synopsys