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Salary
≈ $36k – $72k per year (Estimated)
Location
In office (Yokneam)
Seniority
Intern
Employment
Internship

Confirmed on the employer's own hiring board on Oct 12, 2026. First seen by Alion on Oct 4, 2026. Marvell Technology scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Marvell Technology is an American fabless semiconductor company founded in 1995 that designs the infrastructure silicon behind data centres, carrier networks and storage systems. Its portfolio covers electro-optics and digital signal processors for optical links, ethernet switching and physical layer devices, storage controllers, and custom application specific integrated circuits designed for individual cloud operators. Headquartered in Santa Clara and listed on Nasdaq, it reoriented itself over the past decade from consumer and storage chips toward data centre and artificial intelligence infrastructure, which now supplies the majority of its revenue.

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

We are seeking a motivated and detail-oriented student to join our Design-for-Test (DFT) team as an ATPG (Automatic Test Pattern Generation) Engineer.

This role offers hands-on experience in the development and implementation of test methodologies for complex SoC designs, focusing on scan insertion, pattern generation, and fault coverage analysis.

Interact with IP teams/vendors to resolve all technical verification issues.

Work closely with design/DV/validation/SW teams

What You Can Expect

  • Assist in scan insertion and ATPG flow setup for digital designs.
  • Generate and validate test patterns for stuck-at and transition faults.
  • Analyze fault coverage and identify areas for improvement.
  • Support silicon bring-up and debug of test-related issues.
  • Collaborate with design and verification teams to ensure testability requirements are met.
  • Document methodologies, results, and best practices.

What We're Looking For

  • 2nd/3rd year Student for B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
  • Basic understanding of digital logic design and VLSI concepts.
  • Familiarity with scripting languages (e.g., Python, Perl, or TCL).
  • Exposure to EDA tools such as Synopsys TetraMAX, Cadence Modus, or similar is a plus.
  • Strong analytical and problem-solving skills.
  • Excellent communication and teamwork abilities.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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