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Salary
≈ $123k – $238k per year (Estimated)
Location
In office (San Jose)
Seniority
Staff

Confirmed on the employer's own hiring board on Sep 24, 2026. First seen by Alion on Dec 9, 2025.

Overview
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MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.

The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.

Location: San Jose, CA/Austin, TX/Portland, OR

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