1,711,002open jobs
102,225companies
255,309added this week
Browse all
Salary
≈ $146k – $263k per year (Estimated)
Location
In office (Boxborough)
Seniority
Staff · 10+ years exp

Confirmed on the employer's own hiring board on Oct 16, 2026. First seen by Alion on Aug 24, 2026. Synopsys scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Synopsys is an American software company founded in 1986 that supplies electronic design automation tools used to design and verify integrated circuits, together with a large portfolio of licensable semiconductor IP such as interface, memory and processor blocks. Its 2025 acquisition of Ansys added engineering simulation software for structures, fluids and electromagnetics, while it sold its application security business, now Black Duck, in 2024. Listed on Nasdaq, it hires applications engineers, SoC solutions engineers and R&D staff in the United States, India and Vietnam. The company is headquartered in Sunnyvale, California, United States.

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP. Your expertise encompasses timing closure, power optimization, and design quality across advanced process nodes.

You work effectively across organizational boundaries, collaborating with architecture, analog, verification, and physical design teams. You manage technical tradeoffs systematically, balancing performance, area, and power requirements while maintaining schedule commitments. When faced with evolving specifications, you provide data-driven analysis and practical solutions. At Synopsys, you will contribute to LPDDR PHY IP that powers mobile and AI applications in production silicon worldwide.

What You'll Be Doing

  • Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
  • Optimize designs to meet timing, power, and area targets across multiple process nodes
  • Develop Perl automation for design generation and flow integration
  • Collaborate with cross-functional teams to resolve timing and power challenges
  • Contribute to design reviews and methodology development

The Impact You Will Have

  • Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products
  • You will contribute to a major revenue-generating product line for Synopsys
  • Your work will define performance characteristics for customer systems-on-chip
  • Your automation will improve design efficiency across the engineering team
  • Your expertise will influence architectural decisions for future products

What You'll Need

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 10+ years of ASIC digital design experience with RTL ownership in production silicon
  • Expert Verilog proficiency for timing-critical designs
  • Strong Perl scripting skills for design automation
  • Deep knowledge of synthesis, timing analysis, and power optimization
  • Experience with PHY IP or high-speed interfaces is preferred

Who You Are

  • You understand how RTL structure affects timing and power outcomes
  • You communicate effectively across technical disciplines
  • You produce maintainable code that supports collaboration
  • You identify process improvements proactively
  • You resolve technical issues through systematic analysis

The Team You'll Be Part Of

You will join the team responsible for microarchitecture and front-end design of LPDDR PHY IP. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
1,711,002 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Boxborough
≈ $13k – $32k per year (Estimated) • In office • 5+ years exp • Bengaluru
Python
DevOps
CI/CD
Jenkins
Git
Bitbucket
Management
Confluence
Jira
Agile
QA
Selenium
Apply
≈ $27k – $61k per year (Estimated) • In office • Full-Time • 8+ years exp • Bachelor's Degree • Sanchong
Verilog
VHDL
DevOps
Git
Apply
≈ $29k – $85k per year (Estimated) • In office • Chengdu
C++
SystemVerilog
Chips/EDA
UVM
Apply
≈ $88k – $162k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Plano
Management
Outlook
Microsoft Office
Apply
≈ $108k – $197k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Salem
Apply
≈ $18k – $42k per year (Estimated) • Hybrid • 4+ years exp • Bachelor's Degree • Bengaluru
Python
Verilog
SystemVerilog
TCL Scripting
Chips/EDA
UVM
Apply
Lead MTS Logic Design 1 month ago
≈ $70k – $160k per year (Estimated) • Equity • Hybrid • 7+ years exp • Master's Degree • Aix-en-Provence
Verilog
SystemVerilog
Apply
≈ $56k – $120k per year (Estimated) • In office • Full-Time • 7+ years exp • Bachelor's Degree • Singapore
Verilog
Apply
≈ $32k – $74k per year (Estimated) • In office • Bengaluru
Verilog
SystemVerilog
AI/ML
NVLink
Apply
≈ $20k – $49k per year (Estimated) • In office • Full-Time • 15+ years exp • Bengaluru • Hyderabad • Indore
Java
SQL
Perl
DevOps
Unix
Apply
≈ $145k – $263k per year (Estimated) • In office • 12+ years exp • PhD • Boxborough
Python
Perl
MATLAB
Apply
≈ $140k – $253k per year (Estimated) • In office • 12+ years exp • Bachelor's Degree • Boxborough
Apply
$119k – $179k per year • Equity • Hybrid • 1+ year exp • Bachelor's Degree • Boxborough
Python
Verilog
C++
SystemVerilog
VHDL
DevOps
QEMU
Linux
Windows
Game Dev
DirectX 12
Chips/EDA
UVM
Formal Verification
Synopsys ZeBu
Cadence Palladium
Siemens Veloce
Synopsys HAPS
Cadence Protium
QA
Rest-Assured
Apply
≈ $146k – $263k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Boxborough
Verilog
Perl
Apply
$163k – $244k per year • Equity • In office • 5+ years exp • Bachelor's Degree • Boxborough
Python
Verilog
C++
SystemVerilog
VHDL
Perl
SystemC
AI/ML
AI Agents
DevOps
Linux
Unix
Chips/EDA
UVM
Formal Verification
QA
Rest-Assured
Apply
See all jobs
This is one of many
1,711,002 more open roles from verified company boards, updated every day.