Serdes Digital Design Architect

We are looking for a veteran digital architect who can own and drive the digital subsystems of our next-generation 112 Gb/s-and-beyond Ethernet SerDes.

This role collaborates closely with analog, DSP, firmware, and SoC teams, translating high-level requirements into clean RTL that meets power, performance, and area (PPA) targets-and also guide the design through synthesis, STA, and physical implementation.

Key Responsibilities:

· Define and document the digital micro-architecture for PMA/PMD/PCS blocks, including DSP datapaths and control processors.

-Write high-quality Verilog RTL, verify it (directed + UVM), and debug corner cases across multiple asynchronous clock domains.

· Collaborate daily with analog designers to understand and model mixed-signal effects, ensuring robust digital-on-top flows.

· Craft timing constraints, run STA, and close timing in cutting-edge FinFET nodes.

· Drive lint/CDC/RDC clean-up and formal checks.

· Explore FPGA/prototype platforms to validate algorithms and bring-up firmware pre-silicon.

· Contribute to embedded microcontroller firmware for calibration, adaptation, and link-training routines.

Requirements

Requirements:

· Master's degree or higher in Electrical Engineering

· 10+ years of hands-on experience architecting and implementing high-speed (>32 Gb/s) SerDes or similar high-performance mixed-signal IPs.

· Deep expertise in Verilog/SystemVerilog, synthesis, and STA; familiarity with physical design flows (floor-planning, CTS, routing, IR-drop, EM).

· Proven ability to balance PPA trade-offs and to communicate them clearly to both analog and digital peers.

· Solid grasp of DSP concepts and algorithms (FFE, DFE, CTLE, FEC).

· Working knowledge of the Ethernet protocol stack (IEEE 802.3bs/cd/cg) and PMA/PMD/PCS layer requirements.

· Comfortable with multi-clock-domain design, CDC strategies, and industry-standard verification tools.

· Self-starter who can triage issues across RTL, gate-level netlists, and lab silicon.

• Bonus points for: - FPGA/emulation bring-up experience. - Embedded C/Firmware development for RISC-V or proprietary microcontrollers. - Exposure to advanced process nodes (7 nm, 5 nm, 3 nm)