Senior FPGA RTL and Firmware Development Engineer

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Job Description:

Position Overview

Altera is seeking an experienced FPGA RTL and Firmware Development Engineer to join the Platform Hardware Board Engineering team. This role is intended for a hands-on technical contributor with 10+ years of FPGA RTL design experience and practical firmware development capability. The engineer will own or lead FPGA-based platform solutions spanning RTL architecture, implementation, embedded firmware, system bring-up, validation, and cross-functional debug.

The successful candidate will work closely with FPGA architecture, board design, silicon engineering, software, and Altera development kit teams to deliver robust development kits, validation boards, and platform-level enablement for next-generation Altera FPGA devices.

What You Will Do

• Define, architect, design, implement, and validate FPGA RTL solutions using Verilog and/or VHDL for platform hardware, development kits, and validation boards.

• Lead the complete FPGA development flow, including design planning, simulation, synthesis, implementation, timing analysis, timing closure, configuration, and release readiness using Altera Quartus II tools.

• Develop and maintain embedded firmware in C and/or C++ for FPGA-based systems, with particular emphasis on the Nios II soft-core processor and associated peripherals.

• Use the Altera Embedded Design Suite (EDS) alongside the Altera Quartus II development flow to build, debug, integrate, and validate Nios II-based embedded applications and software components.

• Translate system, functional, and performance requirements into scalable RTL, register maps, firmware interfaces, and verification strategies.

• Support board bring-up, FPGA configuration, hardware-software integration, system initialization, and feature enablement on development and validation platforms.

• Plan and execute simulation, lab validation, stress testing, interoperability testing, and system-level debug using oscilloscopes, logic analyzers, protocol analyzers, and other laboratory equipment.

• Investigate complex issues across RTL, firmware, FPGA timing, board interfaces, clocking, resets, memory, and peripheral integration; drive root-cause analysis and corrective actions.

• Develop reusable RTL blocks, firmware components, test utilities, diagnostic tools, and automation scripts to improve platform development and validation efficiency.

• Collaborate with architecture, board design, silicon, software, applications, and system engineering teams to resolve technical issues and reduce platform risks.

• Review technical designs, RTL, firmware, verification plans, timing reports, lab data, and issue-tracking records; provide technical guidance to less-experienced engineers.

• Document RTL designs, interfaces, test procedures, debug findings, validation results, and release criteria in accordance with Altera engineering standards.

Minimum Qualifications

· Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; advanced degree is a plus.

· 10+ years of professional experience in FPGA RTL design, implementation, and system-level validation.

· Strong hands-on experience with Verilog and/or VHDL, digital logic design, computer architecture, clock-domain crossing, reset design, and FPGA-based system integration.

· Proven experience with the Altera Quartus II FPGA development flow, including simulation, synthesis, implementation, timing analysis, timing closure, and device programming.

· Working knowledge of C and/or C++ for embedded firmware, hardware-software integration, diagnostics, or platform validation.

· Experience developing or integrating firmware for the Nios II soft-core processor, including peripheral access, interrupt handling, memory-mapped I/O, drivers, or board-support software.

· Practical experience with the Altera Embedded Design Suite (EDS) for Nios II software development, build, debug, and integration.

· Demonstrated ability to bring up and debug FPGA development boards or complex hardware platforms using lab equipment and structured debug methods.

· Strong analytical, problem-solving, communication, and technical documentation skills.

· Ability to work effectively across global, cross-functional engineering teams and independently drive deliverables to completion.

Preferred Qualifications

· Experience with Nios II system architecture, Platform Designer/Qsys integration, custom IP, Avalon interfaces, DMA, memory controllers, and peripheral subsystems.

· Experience creating RTL-to-firmware interfaces, register specifications, device drivers, diagnostics, and automated validation tools.

· Knowledge of FPGA configuration, boot flows, JTAG, PCIe, Ethernet, DDR memory, high-speed serial interfaces, or other board-level interfaces.

· Familiarity with SystemVerilog, assertion-based verification, or other modern verification techniques.

· Experience with Python, Tcl, or similar scripting languages for build automation, regression, test execution, report generation, and lab automation and Agentic AI knowledge for massive efficiency improvements.

· Experience with version-control systems, continuous integration, code review, issue tracking, and disciplined hardware/software release processes.

· Experience leading technical reviews, mentoring engineers, coordinating cross-functional debug, and communicating status and risks to program stakeholders.

Qualifications:

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; advanced degree is a plus.

• 10+ years of professional experience in FPGA RTL design, implementation, and system-level validation.

• Strong hands-on experience with Verilog and/or VHDL, digital logic design, computer architecture, clock-domain crossing, reset design, and FPGA-based system integration.

• Proven experience with the Altera Quartus II FPGA development flow, including simulation, synthesis, implementation, timing analysis, timing closure, and device programming.

• Working knowledge of C and/or C++ for embedded firmware, hardware-software integration, diagnostics, or platform validation.

• Experience developing or integrating firmware for the Nios II soft-core processor, including peripheral access, interrupt handling, memory-mapped I/O, drivers, or board-support software.

• Practical experience with the Altera Embedded Design Suite (EDS) for Nios II software development, build, debug, and integration.

• Demonstrated ability to bring up and debug FPGA development boards or complex hardware platforms using lab equipment and structured debug methods.

• Strong analytical, problem-solving, communication, and technical documentation skills.

• Ability to work effectively across global, cross-functional engineering teams and independently drive deliverables to completion.

Preferred Qualifications

• Experience with Nios II system architecture, Platform Designer/Qsys integration, custom IP, Avalon interfaces, DMA, memory controllers, and peripheral subsystems.

• Experience creating RTL-to-firmware interfaces, register specifications, device drivers, diagnostics, and automated validation tools.

• Knowledge of FPGA configuration, boot flows, JTAG, PCIe, Ethernet, DDR memory, high-speed serial interfaces, or other board-level interfaces.

• Familiarity with SystemVerilog, assertion-based verification, or other modern verification techniques.

• Experience with Python, Tcl, or similar scripting languages for build automation, regression, test execution, report generation, and lab automation and Agentic AI knowledge for massive efficiency improvements.

• Experience with version-control systems, continuous integration, code review, issue tracking, and disciplined hardware/software release processes.

• Experience leading technical reviews, mentoring engineers, coordinating cross-functional debug, and communicating status and risks to program stakeholders.

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