Senior Design Lead

Job Summary

We are seeking a Senior Design Verification Engineer with 8 to 15 years of experience in ASIC/SoC verification and deep expertise in one or more next-generation technologies such as PCIe Gen5/Gen6, LPDDR5/LPDDR6, HBM3/HBM4, UCIe, Ethernet, ARM Neoverse, CHI, and advanced SoC interconnects. The candidate will be responsible for developing robust verification environments, driving verification closure, and contributing to complex IP, subsystem, and SoC-level verification programs.

Key Responsibilities

Key Responsibilities

• Develop and maintain reusable SystemVerilog/UVM based verification environments.
• Create verification plans, test cases, sequences, scoreboards, and checkers.
• Develop constrained-random and directed tests to validate complex protocol and architectural features.
• Implement functional coverage models and SystemVerilog Assertions (SVA).
• Execute regressions, analyze failures, and drive verification closure.
• Debug complex simulation failures and identify design versus testbench issues.
• Collaborate closely with Architecture, RTL Design, Firmware, and Validation teams.
• Contribute to SoC-level integration and performance verification.

Required Skills

• Strong hands-on experience in SystemVerilog, UVM/OVM, Assertions (SVA), and Functional Coverage.
• Solid understanding of ASIC/SoC verification methodologies and verification lifecycle.
• Experience in protocol verification, testbench architecture, test development, and debug.
• Knowledge of C/C++ and scripting (Python/Perl/Shell/TCL).

Skill Requirements

Niche Expertise (One or More of the Following)

High-Speed Interfaces & Memory

• PCIe Gen5/Gen6
• CXL 2.0/3.0
• UCIe
• LPDDR5/LPDDR6
• HBM2E/HBM3/HBM4
• DDR5
• Ethernet (100G/400G/800G)
• USB4
• MIPI (CSI/DSI)

ARM & Coherency Architectures

• ARM Neoverse platforms
• AMBA AXI/AHB/APB
• ARM CHI / CHI-E
• CMN (Coherent Mesh Network)
• CCIX
• Cache Coherency Verification
• Multi-core CPU subsystem verification

AI/HPC & Advanced SoC Technologies

• AI/ML Accelerator Verification
• NPU/GPU Verification
• Network-on-Chip (NoC)
• High-Performance Computing (HPC) SoCs
• Data Center / Cloud Infrastructure SoCs
• RAS (Reliability, Availability, Serviceability)
• Security and TrustZone Verification
• Power Management & Low-Power Verification (UPF/CPF)

Preferred Skills

• Formal Verification exposure.
• Emulation/FPGA prototyping experience.
• Experience with Synopsys VIP, Cadence VIP, or Siemens VIP.
• Knowledge of performance modeling and system-level verification.
• Experience with Verdi, DVE, SimVision, VCS, Xcelium, or Questa.

Other Requirements