LPDDR PHY IP Verification Engineer--18743

Synopsys • English • EDA Software • Application Security • Verilog • SystemVerilog • 5 days ago
Apply now
Similar jobs
1,008,666open jobs
59,992companies
167,270added this week
Browse all
Salary
≈ $30k – $70k per year (Estimated)
Location
In office (Wuhan)
Seniority
Senior · 6+ years exp

Confirmed on the employer's own hiring board on Oct 1, 2026. First seen by Alion on Sep 26, 2026. Synopsys scores A on the Alion truth index.

Overview
Company
Impact
Profile match

Synopsys

Synopsys (NASDAQ: SNPS) is a premier American multinational technology corporation and the global leader in Electronic Design Automation (EDA), semiconductor intellectual property (IP), and software security and quality solutions. Headquartered in Sunnyvale, California, and led by CEO Sassine Ghazi, Synopsys operates on a B2B enterprise software, proprietary semiconductor IP licensing, and silicon engineering services model.
synopsys.com • HQ: Sunnyvale, United States • Application Security • Semiconductor IP & Chip Design Services • EDA Software • 5000+ employees
Tech stack of Synopsys

Job Description and Requirements

Our LPDDR PHY IP team is looking to add a Digital ASIC Verification Engineer to our team. In this role you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers.

Key Qualifications

  • BSEE in EE with 6+ years of relevant experience or MSEE with 3+ years of relevant experience
  • Experience in ASIC RTL design and verification at the chip level and block level
  • Strong Verilog, system Verilog, UVM, PERL, and TCL skills
  • Knowledge in silicon debugging
  • Demonstrates good communication skills in both Mandarin and English
  • Demonstrates good analysis and problem-solving skills
  • Knowledge of high speed interface protocols is a plus

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
1,008,666 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Wuhan
≈ $38k – $79k per year (Estimated) • In office • 5+ years exp • Shenzhen
DevOps
Linux
Apply
≈ $23k – $65k per year (Estimated) • In office • Shenzhen
Chips/EDA
Cadence Allegro
OrCAD
Apply
≈ $27k – $77k per year (Estimated) • In office • Full-Time • Shanghai
Python
C#
Management
Microsoft Office
Apply
≈ $27k – $77k per year (Estimated) • In office • Full-Time • Shanghai
Python
C#
Management
Microsoft Office
Apply
≈ $49k – $116k per year (Estimated) • In office • Full-Time • 5+ years exp • Shanghai
Verilog
SystemVerilog
VHDL
DevOps
Linux
Unix
Chips/EDA
UVM
Cadence Palladium
Cadence Protium
Apply
≈ $65k – $154k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Reading
Verilog
SystemVerilog
Chips/EDA
UVM
Apply
≈ $36k – $82k per year (Estimated) • In office • 15+ years exp • Hsinchu
Python
Verilog
SystemVerilog
Perl
Chips/EDA
UVM
Apply
≈ $113k – $260k per year (Estimated) • In office • Full-Time • 5+ years exp • Bachelor's Degree • Seattle
Verilog
SystemVerilog
Chips/EDA
Cadence Virtuoso
Apply
≈ $94k – $185k per year (Estimated) • In office • 3+ years exp • Bachelor's Degree • Herndon
Verilog
SystemVerilog
VHDL
AI/ML
OpenCL
DevOps
Linux
Management
Agile
Scrum
Apply
Sr Consultant 5 days ago
In office
Verilog
C++
Chips/EDA
Synopsys VCS
UVM
Apply
≈ $40k – $84k per year (Estimated) • In office • 6+ years exp • Wuhan
Python
Verilog
SystemVerilog
Perl
Chips/EDA
Synopsys SpyGlass
Synopsys Verdi
Apply
≈ $38k – $88k per year (Estimated) • In office • 8+ years exp • Shanghai
Verilog
SystemVerilog
Apply
≈ $65k – $154k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Reading
Verilog
SystemVerilog
Chips/EDA
UVM
Apply
≈ $36k – $82k per year (Estimated) • In office • 15+ years exp • Hsinchu
Python
Verilog
SystemVerilog
Perl
Chips/EDA
UVM
Apply
In office • 5+ years exp • Bachelor's Degree
Python
Verilog
Perl
Apply
≈ $24k – $55k per year (Estimated) • In office • 3+ years exp • Wuhan
Python
Verilog
Perl
Apply
≈ $22k – $63k per year (Estimated) • In office • Full-Time • Wuhan
C++
C++
Qt
Apply
In office • Full-Time • 1+ year exp • Wuhan
Management
Microsoft Office
Apply
≈ $22k – $53k per year (Estimated) • In office • Full-Time • 4+ years exp • Bachelor's Degree • Beijing • Wuhan • Guangzhou • Shanghai
DevOps
GCP
Apply
In office • Full-Time • 2+ years exp • Wuhan
DevOps
Linux
Apply
See all jobs
This is one of many
1,008,666 more open roles from verified company boards, updated every day.
Browse all jobs Get matched roles